323 lines
13 KiB
Rust
323 lines
13 KiB
Rust
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#![no_std]
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#![no_main]
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use core::fmt::{self, Write};
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use core::hint::spin_loop;
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use core::ptr::{read_volatile, write_volatile};
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use panic_halt as _;
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use riscv_rt::entry;
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use esp_p4_eth::{
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mdio_read, release_waveshare_phy_reset, Dma, Ethernet, StaticDmaResources, ANAR, ANLPAR,
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BMCR, BMSR, BUF_SIZE, PHYIDR1, PHYIDR2,
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};
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use static_cell::ConstStaticCell;
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const UART0_BASE: usize = 0x500C_A000;
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const UART_FIFO_REG: *mut u32 = UART0_BASE as *mut u32;
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const UART_STATUS_REG: *const u32 = (UART0_BASE + 0x1C) as *const u32;
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const UART_TXFIFO_CNT_SHIFT: u32 = 16;
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const UART_TXFIFO_CNT_MASK: u32 = 0xFF << UART_TXFIFO_CNT_SHIFT;
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const UART_TXFIFO_CAPACITY: u32 = 128;
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const MAC_ADDR: [u8; 6] = [0x02, 0x00, 0x00, 0x00, 0x00, 0x01];
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// Peer-to-peer link with PC. Windows has APIPA 169.254.144.33/16 on the Realtek port.
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const SENDER_IP: [u8; 4] = [169, 254, 144, 50];
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const TARGET_IP: [u8; 4] = [169, 254, 144, 33];
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const BROADCAST_MAC: [u8; 6] = [0xFF; 6];
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const LINK_POLL_SPINS: usize = 200_000;
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const RX_POLL_SPINS: usize = 200_000;
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static DMA_RESOURCES: ConstStaticCell<StaticDmaResources> =
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ConstStaticCell::new(StaticDmaResources::new());
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struct Uart0;
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impl Uart0 {
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fn write_byte(&mut self, byte: u8) {
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while txfifo_count() >= UART_TXFIFO_CAPACITY {
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spin_loop();
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}
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// SAFETY: `UART_FIFO_REG` is the fixed UART0 TX FIFO MMIO register. Volatile write is
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// required so the compiler preserves the hardware side effect.
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unsafe {
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write_volatile(UART_FIFO_REG, byte as u32);
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}
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}
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}
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impl Write for Uart0 {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for byte in s.bytes() {
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if byte == b'\n' {
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self.write_byte(b'\r');
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}
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self.write_byte(byte);
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}
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Ok(())
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}
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}
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#[entry]
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fn main() -> ! {
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let mut uart = Uart0;
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let _ = writeln!(uart, "EMAC raw PHY smoke test");
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release_waveshare_phy_reset();
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delay_cycles(3_000_000);
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let dma_resources = DMA_RESOURCES.take();
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let ethernet = Ethernet::new_from_static_resources(MAC_ADDR, dma_resources);
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let mut ethernet = ethernet;
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// RETRY hypothesis #2 with fixed pin routing: now OUT_SEL=256, peripheral-direct path is
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// active. start() may now have a real effect.
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let _ = writeln!(uart, "calling ethernet.start()...");
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match ethernet.start() {
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Ok(()) => { let _ = writeln!(uart, " start() OK"); }
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Err(e) => { let _ = writeln!(uart, " start() ERR: {:?}", e); }
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}
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delay_cycles(2_000_000);
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// GPIO matrix / IO_MUX / GPIO_ENABLE diagnostic dump for MDC/MDIO/REF_CLK.
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unsafe {
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const GPIO_BASE: usize = 0x500E_0000;
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const IO_MUX_BASE: usize = 0x500E_1000;
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let rd = |a: usize| read_volatile(a as *const u32);
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let _ = writeln!(uart, "--- routing dump ---");
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let _ = writeln!(uart, "IO_MUX_GPIO31 = 0x{:08X}", rd(IO_MUX_BASE + 4 + 31 * 4));
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let _ = writeln!(uart, "IO_MUX_GPIO52 = 0x{:08X}", rd(IO_MUX_BASE + 4 + 52 * 4));
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let _ = writeln!(uart, "IO_MUX_GPIO50 = 0x{:08X}", rd(IO_MUX_BASE + 4 + 50 * 4));
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let _ = writeln!(uart, "GPIO31_OUT_CFG = 0x{:08X}", rd(GPIO_BASE + 0x554 + 31 * 4));
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let _ = writeln!(uart, "GPIO52_OUT_CFG = 0x{:08X}", rd(GPIO_BASE + 0x554 + 52 * 4));
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let _ = writeln!(uart, "GPIO_FUNC107_IN= 0x{:08X}", rd(GPIO_BASE + 0x154 + 107 * 4));
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let _ = writeln!(uart, "GPIO_FUNC108_IN= 0x{:08X}", rd(GPIO_BASE + 0x154 + 108 * 4));
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let _ = writeln!(uart, "GPIO_FUNC109_IN= 0x{:08X}", rd(GPIO_BASE + 0x154 + 109 * 4));
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let en0 = rd(GPIO_BASE + 0x20);
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let en1 = rd(GPIO_BASE + 0x2C);
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let _ = writeln!(uart, "GPIO_ENABLE0 = 0x{:08X} (bit31 MDC = {})", en0, (en0 >> 31) & 1);
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let _ = writeln!(uart, "GPIO_ENABLE1 = 0x{:08X} (bit20 MDIO52 = {})", en1, (en1 >> (52 - 32)) & 1);
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// GPIO_OUT (level register) — bit per pin. Pin 51 RESET should be HIGH for IP101 to run.
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let out0 = rd(GPIO_BASE + 0x04);
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let out1 = rd(GPIO_BASE + 0x10);
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let _ = writeln!(uart, "GPIO_OUT0 = 0x{:08X}", out0);
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let _ = writeln!(uart, "GPIO_OUT1 = 0x{:08X} (bit19 RESET51 level = {})", out1, (out1 >> (51 - 32)) & 1);
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// GPIO_IN — what the pin actually reads (after pad mux). For pin 50 (REF_CLK) high
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// bit means the clock is currently high; toggling = clock running.
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let in0 = rd(GPIO_BASE + 0x3C);
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let in1 = rd(GPIO_BASE + 0x44);
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let _ = writeln!(uart, "GPIO_IN0 = 0x{:08X}", in0);
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let _ = writeln!(uart, "GPIO_IN1 = 0x{:08X} (bit18 REFCLK50 = {})", in1, (in1 >> (50 - 32)) & 1);
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// Sample REFCLK50 (GPIO50, bit18 in IN1) many times. If a 50 MHz clock is running,
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// we should see a mix of 0 and 1. If it's stuck high or low — clock is dead.
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let mut zeros = 0u32;
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let mut ones = 0u32;
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for _ in 0..200 {
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let v = rd(GPIO_BASE + 0x44);
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if (v >> 18) & 1 == 0 { zeros += 1; } else { ones += 1; }
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}
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let _ = writeln!(uart, "REFCLK50 sample: zeros={} ones={} (over 200 reads)", zeros, ones);
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// Same for MDC pin (GPIO31, bit31 in IN0). MDC only pulses during MDIO transactions
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// (and we're idle right now), so it's expected to be near-constant. But if we see
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// ones or transitions, then peripheral OE works and pin can drive.
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let mut mdc_zeros = 0u32;
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let mut mdc_ones = 0u32;
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for _ in 0..200 {
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let v = rd(GPIO_BASE + 0x3C);
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if (v >> 31) & 1 == 0 { mdc_zeros += 1; } else { mdc_ones += 1; }
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}
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let _ = writeln!(uart, "MDC31 sample: zeros={} ones={} (idle, expect mostly low)", mdc_zeros, mdc_ones);
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// EMAC MII_ADDR — CSR_CLOCK_RANGE field is bits[5:2]; show full reg.
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// EMAC_BASE on P4 = 0x5009_8000, MII_ADDR offset = 0x10.
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let mii_addr = rd(0x5009_8010);
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let _ = writeln!(uart, "EMAC MII_ADDR = 0x{:08X} (csr_clk_range = 0b{:04b})",
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mii_addr, (mii_addr >> 2) & 0xF);
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}
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// Drive ONE explicit mdio_read for addr 0 / BMSR and dump the post-state of MII_ADDR
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// and MII_DATA. This tells us whether the transaction actually completes (MII_BUSY
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// clears) and what the data register reads back. If BUSY stays set => MDC clock or
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// peripheral state issue. If BUSY=0 but data=0 => bus driven low (EMAC or floating).
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{
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let v = mdio_read(0, BMSR).unwrap_or(0xDEAD);
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let mii_addr_after = unsafe { read_volatile(0x5009_8010 as *const u32) };
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let mii_data_after = unsafe { read_volatile(0x5009_8014 as *const u32) };
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let _ = writeln!(uart, "single read addr=0 reg=BMSR -> 0x{:04X}", v);
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let _ = writeln!(uart, " MII_ADDR after = 0x{:08X} (BUSY={})", mii_addr_after, mii_addr_after & 1);
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let _ = writeln!(uart, " MII_DATA after = 0x{:08X}", mii_data_after);
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}
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// MDIO scan to confirm PHY address + bus health.
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let mut found = 0xFFu8;
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for addr in 0u8..32 {
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let v = mdio_read(addr, BMSR).unwrap_or(0xDEAD);
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let live = v != 0x0000 && v != 0xFFFF && v != 0xDEAD;
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if live {
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let _ = writeln!(uart, " scan addr={:>2} BMSR=0x{:04X} <- live", addr, v);
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if found == 0xFF { found = addr; }
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}
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}
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if found == 0xFF {
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let _ = writeln!(uart, " scan: NO live PHY addresses found");
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found = 0;
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}
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let id1 = mdio_read(found, PHYIDR1).unwrap_or(0xDEAD);
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let id2 = mdio_read(found, PHYIDR2).unwrap_or(0xDEAD);
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let bmcr = mdio_read(found, BMCR).unwrap_or(0xDEAD);
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let bmsr = mdio_read(found, BMSR).unwrap_or(0xDEAD);
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let anar = mdio_read(found, ANAR).unwrap_or(0xDEAD);
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let anlpar = mdio_read(found, ANLPAR).unwrap_or(0xDEAD);
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let _ = writeln!(uart, "PHY@{} regs: ID1=0x{:04X} ID2=0x{:04X} BMCR=0x{:04X} BMSR=0x{:04X} ANAR=0x{:04X} ANLPAR=0x{:04X}",
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found, id1, id2, bmcr, bmsr, anar, anlpar);
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let _ = writeln!(uart, "BMSR decoded: link={} an_done={}", (bmsr >> 2) & 1, (bmsr >> 5) & 1);
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let _ = writeln!(uart, "Waiting for link up (poll BMSR)...");
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let mut link_up = false;
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let mut last_bmsr = bmsr;
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for iter in 0..60u32 {
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let v = mdio_read(found, BMSR).unwrap_or(0xDEAD);
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if v != last_bmsr {
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let _ = writeln!(uart, "[{iter}] BMSR 0x{:04X} -> 0x{:04X} link={} an_done={}",
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last_bmsr, v, (v >> 2) & 1, (v >> 5) & 1);
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last_bmsr = v;
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}
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if v & 0x0004 != 0 {
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link_up = true;
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let _ = writeln!(uart, "[{iter}] LINK UP", );
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break;
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}
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delay_cycles(LINK_POLL_SPINS);
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}
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if !link_up {
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let _ = writeln!(uart, "link still down after 60 polls (last BMSR=0x{:04X}); starting MAC anyway", last_bmsr);
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}
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let _ = writeln!(uart, "ethernet.start()...");
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ethernet.start().expect("failed to start EMAC");
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let _ = writeln!(uart, "phy_negotiate()...");
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let (speed, duplex) = ethernet.phy_negotiate().expect("PHY negotiation failed");
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log_link_mode(&mut uart, speed, duplex);
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let mut arp_request = [0u8; 64];
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let arp_len = build_arp_request(&mut arp_request, MAC_ADDR, SENDER_IP, TARGET_IP);
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ethernet
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.transmit(&arp_request[..arp_len])
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.expect("failed to send ARP request");
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let _ = writeln!(uart, "ARP request sent");
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let mut rx_frame = [0u8; BUF_SIZE];
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let mut echo_frame = [0u8; BUF_SIZE];
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loop {
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Dma::demand_rx_poll();
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if let Some(len) = wait_for_frame(&mut ethernet, &mut rx_frame) {
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log_frame(&mut uart, "rx", &rx_frame[..len]);
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if len >= 14 {
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let echo_len = build_echo_frame(&mut echo_frame, &rx_frame[..len], MAC_ADDR);
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ethernet
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.transmit(&echo_frame[..echo_len])
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.expect("failed to echo frame");
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let _ = writeln!(uart, "echo sent: len={echo_len}");
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}
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}
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}
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}
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fn wait_for_frame(ethernet: &mut Ethernet<'_>, rx_frame: &mut [u8; BUF_SIZE]) -> Option<usize> {
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for _ in 0..RX_POLL_SPINS {
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if let Some((len, data)) = ethernet.receive() {
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rx_frame[..len].copy_from_slice(&data[..len]);
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ethernet.pop_rx();
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return Some(len);
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}
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spin_loop();
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}
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None
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}
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fn build_arp_request(
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frame: &mut [u8; 64],
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source_mac: [u8; 6],
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sender_ip: [u8; 4],
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target_ip: [u8; 4],
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) -> usize {
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frame.fill(0);
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frame[0..6].copy_from_slice(&BROADCAST_MAC);
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frame[6..12].copy_from_slice(&source_mac);
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frame[12..14].copy_from_slice(&0x0806u16.to_be_bytes());
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frame[14..16].copy_from_slice(&0x0001u16.to_be_bytes());
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frame[16..18].copy_from_slice(&0x0800u16.to_be_bytes());
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frame[18] = 6;
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frame[19] = 4;
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frame[20..22].copy_from_slice(&0x0001u16.to_be_bytes());
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frame[22..28].copy_from_slice(&source_mac);
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frame[28..32].copy_from_slice(&sender_ip);
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frame[32..38].fill(0);
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frame[38..42].copy_from_slice(&target_ip);
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64
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}
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fn build_echo_frame(out: &mut [u8; BUF_SIZE], input: &[u8], source_mac: [u8; 6]) -> usize {
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let len = input.len();
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out[..len].copy_from_slice(input);
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out[0..6].copy_from_slice(&input[6..12]);
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out[6..12].copy_from_slice(&source_mac);
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len
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}
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fn log_link_mode(uart: &mut Uart0, speed: esp_p4_eth::Speed, duplex: esp_p4_eth::Duplex) {
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let speed_str = match speed {
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esp_p4_eth::Speed::Mbps10 => "10M",
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esp_p4_eth::Speed::Mbps100 => "100M",
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};
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let duplex_str = match duplex {
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esp_p4_eth::Duplex::Half => "half",
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esp_p4_eth::Duplex::Full => "full",
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};
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let _ = writeln!(uart, "link up: speed={speed_str} duplex={duplex_str}");
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}
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fn log_frame(uart: &mut Uart0, prefix: &str, frame: &[u8]) {
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if frame.len() < 14 {
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let _ = writeln!(uart, "{prefix}: short frame len={}", frame.len());
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return;
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}
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let dst = &frame[0..6];
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let src = &frame[6..12];
|
||
|
|
let ether_type = u16::from_be_bytes([frame[12], frame[13]]);
|
||
|
|
|
||
|
|
let _ = writeln!(
|
||
|
|
uart,
|
||
|
|
"{prefix}: len={} dst={:02x}:{:02x}:{:02x}:{:02x}:{:02x}:{:02x} src={:02x}:{:02x}:{:02x}:{:02x}:{:02x}:{:02x} ethertype=0x{:04x}",
|
||
|
|
frame.len(),
|
||
|
|
dst[0], dst[1], dst[2], dst[3], dst[4], dst[5],
|
||
|
|
src[0], src[1], src[2], src[3], src[4], src[5],
|
||
|
|
ether_type
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
fn delay_cycles(spins: usize) {
|
||
|
|
for _ in 0..spins {
|
||
|
|
spin_loop();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
fn txfifo_count() -> u32 {
|
||
|
|
// SAFETY: `UART_STATUS_REG` is the fixed UART0 status MMIO register. Volatile read is
|
||
|
|
// required because the value changes independently from the CPU.
|
||
|
|
let status = unsafe { read_volatile(UART_STATUS_REG) };
|
||
|
|
(status & UART_TXFIFO_CNT_MASK) >> UART_TXFIFO_CNT_SHIFT
|
||
|
|
}
|