69 lines
1.9 KiB
Rust
69 lines
1.9 KiB
Rust
#![no_std]
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#![no_main]
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use core::fmt::{self, Write};
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use core::hint::spin_loop;
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use core::ptr::{read_volatile, write_volatile};
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use panic_halt as _;
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use riscv_rt::entry;
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use esp_p4_eth::{configure_clock_ext_in, regs, RefClockPin};
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const UART0_BASE: usize = 0x500C_A000;
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const UART_FIFO_REG: *mut u32 = UART0_BASE as *mut u32;
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const UART_STATUS_REG: *const u32 = (UART0_BASE + 0x1C) as *const u32;
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const UART_TXFIFO_CNT_SHIFT: u32 = 16;
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const UART_TXFIFO_CNT_MASK: u32 = 0xFF << UART_TXFIFO_CNT_SHIFT;
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const UART_TXFIFO_CAPACITY: u32 = 128;
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struct Uart0;
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impl Uart0 {
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fn write_byte(&mut self, byte: u8) {
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while txfifo_count() >= UART_TXFIFO_CAPACITY {
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spin_loop();
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}
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// SAFETY: `UART_FIFO_REG` is the fixed UART0 TX FIFO MMIO register. Volatile write is
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// required so the compiler preserves the hardware side effect.
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unsafe {
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write_volatile(UART_FIFO_REG, byte as u32);
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}
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}
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}
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impl Write for Uart0 {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for byte in s.bytes() {
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if byte == b'\n' {
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self.write_byte(b'\r');
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}
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self.write_byte(byte);
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}
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Ok(())
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}
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}
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#[entry]
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fn main() -> ! {
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configure_clock_ext_in(RefClockPin::Gpio32);
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// SAFETY: `VERSION_ADDR` is the documented EMAC version register. Volatile read is required
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// because MMIO values are not ordinary memory.
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let version = unsafe { read_volatile(regs::mac::VERSION_ADDR as *const u32) };
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let mut uart = Uart0;
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let _ = writeln!(uart, "EMAC_VERSION = 0x{version:08X}");
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loop {
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spin_loop();
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}
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}
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fn txfifo_count() -> u32 {
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// SAFETY: `UART_STATUS_REG` is the fixed UART0 status MMIO register. Volatile read is
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// required because the value changes independently from the CPU.
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let status = unsafe { read_volatile(UART_STATUS_REG) };
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(status & UART_TXFIFO_CNT_MASK) >> UART_TXFIFO_CNT_SHIFT
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}
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