tonycao/ethercat-linux
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8dca6395d0
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13 Commits

Author SHA1 Message Date
Tony Cao
8dca6395d0 feat(rfm): add rfm-ring mode for one-shot PCIe ring-continuity check 2026-09-24 15:34:25 +08:00
Tony Cao
3f29a86239 rfm-bridge: fix FPWR gating (was inside Mode::Ticker so bridge never wrote SM2), single-point f(x) on D2000, dumb reflector echo, REP budget 1.5ms 2026-09-24 15:12:43 +08:00
Tony Cao
b92484a86c rfm: multi-card --rfm-dev, ARM64 device-memory-safe bulk I/O, RT pinning, mailbox init 
- Rfm::open_path() for selecting /dev/rfm2gN on multi-card hosts
  (verified on D2000 dual PCI-5565: rfm2g0/rfm2g1)
- dev_read/dev_write: aligned volatile word/byte loops for bulk payload
  access. memcpy/memset on non-cached (DEVICE_nGnRnE) mappings faults
  with SIGBUS on ARM64 - root cause of the ping crash, verified fixed
- rfm_mode_main: RT-promote onto cfg.core (ping/echo spinning on the
  same core added ~0.5ms scheduling latency), clear REQ/REP mailbox
  headers at startup so stale data cannot poison first RTT samples
- ping S-line: dseq (req-rep sequence lag) instrumentation
- remove vendor/crc32fast/.gitignore from index
 2026-09-21 19:02:20 +08:00
Tony Cao
e032f31392 feat(rfm): PCI-5565 reflective memory via VFIO/kernel-driver, ping/echo/bridge modes 
- src/rfm.rs: dual backend (rfm2g chardev /dev/rfm2g0 or vfio-pci BAR mmap),
  mailbox protocol (REQ@0x0/REP@0x1000, seq release/acquire)
- --mode rfm-ping: periodic REQ write + spin-wait REP, same-clock RTT histogram
- --mode rfm-echo: REQ->REP reflector; CX frames (>=280B) get f(x)=x*7+3
  transform so PLC echo check passes through the RFM hop
- --mode rfm-bridge: EL6695 RX -> RFM -> remote J1900 processing -> EL6695 TX
  with per-second bridge counters and rfm_hop_rtt stats (end-to-end
  CX->EL6695->D2000->RFM->x86 latency measurement)
- OnlineStats: public mean() accessor
 2026-09-20 13:03:16 +08:00
Tony Cao
4083df04fb RTT optimization: 8kHz support, io_uring backend option (tested slower), RT-promote tx_rx thread; 8kHz RTT min 0.75ms mean 1.04ms 2026-08-12 21:47:50 +08:00
Tony Cao
253f4b3cf7 J1900-side DC-Synchron: EL6695 secondary firmware sync_mode=2 via CoE, DC telemetry, verified 180s zero sync errors 2026-08-10 01:56:41 +08:00
Tony Cao
cdb90c3e9a Extend async pipelined FPWR to 800B: 4kHz spin loop 2040->2960 cycles/s 2026-08-10 01:28:43 +08:00
Tony Cao
f0163d8d70 800B PDO variant + long-term stability evidence + analysis docs 
- twin_layout_blob_sized generalized: multi-entry TwinCAT line format
  (1 real @240bit + N continuation + remainder entry); 1024B path kept
  byte-identical; 800B = 27 entries verified on hardware
- 800B constants (PAYLOAD/SM 800), deployed as el6695_rt_800b
- 10-min + 5h stability runs: 18M cycles, zero errors, zero mismatches,
  PLC nMismatch frozen over the whole run (monitor_5h.csv evidence)
- docs: 800B plan/design/verification/test-report chapters,
  jitter analysis (NFS rootfs stall primary cause), D2000 dev plan
- scripts: 800B deploy/relink/verify, mismatch-delta, 5h monitor
 2026-08-06 01:10:50 +08:00
Tony Cao
8c1f519526 Async pipelined FPWR + 4kHz: exec 245us->24us, RTT 2ms->1.25-1.5ms 
- FPWR fire-and-forget: two alternating leaked tx slots, or()-driven
  20us kick to reach sendable, poll_once reap after next spin-detect
  (late=0 over 350k cycles). Fixes: reap placement, poll_once kick
- exec drops to 24us mean, freeing budget for 4kHz (250us) operation
- 4kHz verified: TwinCAT PLC at 4001.8Hz, lag 5-6 cycles
  (RTT 1.25-1.5ms); J1900 effective 2.9kHz - FPRD poll cost (71us x N)
  exceeds 250us budget, occasional frame miss
- Conclusion: J1900 write wait never contributed to lag; the 4-stage
  pipeline is TwinCAT IO mapping + bridge forwarding
 2026-07-28 01:18:05 +08:00
Tony Cao
3a26aea082 2kHz spin-lock mode: RTT halved to 2ms, per-byte XOR proof at 500us cycle 
- ticker: --spin mode polls FPRD until payload changes (phase-locks
  processing to TwinCAT frame arrival instead of free-running ticker),
  timeout at 1.5 periods keeps loop alive on master stop
- verified: 238k cycles, 0 errors, exec=245us (FPWR-bound),
  TwinCAT PLC task confirmed at 2000.8 Hz (all three tasks 0.5ms;
  base tick was already 50us - no base-time change needed)
- docs: 500us latency plan; scripts: task-rate ADS probe, 2kHz deploy,
  UI automation experiments (pywinauto) for task cycle inspection
 2026-07-28 00:11:34 +08:00
Tony Cao
309aaba342 EL6695 8-byte bidirectional exchange with per-byte verification 
- 8B PDO config: ULINT-sized payload, no 0x1A01 diag PDO on SM3
  (device rejected SM3=8 with diag assigned: 'size not allowed, min/max 0xa')
- twin_layout_blob_sized(): single 64-bit mapping entry for 8B payloads
- Ticker: per-byte XOR 0x5A transform in 8B mode so TwinCAT can verify
  every byte individually (1KB path unchanged, const-guarded)
- TwinCAT automation scripts: deploy with RPC retry, LinkVariables-based
  whole-array relink (element links only carry 1 byte), ADS watch, diag
- Docs: 8B design, verification methodology, test report
 2026-07-27 19:01:05 +08:00
Tony Cao
2837f2a13d EL6695 secondary side: SAFEOP/OP bring-up + 1kHz data loop 
- Fix SM ctrl bytes for SM2 (0x64) and SM3 (0x20) per ESI
- Add SM2/SM3 register config + FMMU + PDO assignment via SDO
- Change SM_TX_ADDR/RX_ADDR to SM2(0x1C00)/SM3(0x8E00)
- Add ensure_od_secondary for PDO assignment
- Add secondary-side diagnostics (CoE object probe)
- Update SM2/SM3 enable/disable sequence for clean config
- Add full bring-up sequence: INIT->PREOP->SAFEOP->OP
 2026-07-23 00:46:48 +08:00
Tony Cao
21b2d3bf99 J1900 <-> TwinCAT 1 kHz verification over EL6695 bridge 
Re-implementation of rustbootd's ecat_el6695_* examples as a single binary
with fixes found in review and on hardware:

- DC-follow PLL hardened against period-2 hunting: slew-limited anchor
  (+/-50us/cycle), bistable-trap snap re-anchor, re-prime on stale deadline
- drift-free absolute-grid ticker mode; probe mode for timestamp forensics
- bounded-memory online stats (histograms), graceful SIGINT/SIGTERM shutdown
  with full report, error-streak abort
- timestamp plausibility filter comparing against the previous raw sample
  (avoids the deadlock after a startup outlier)
- XFC scope waveform options: --el2202 (with --el2202-dual), --el2262,
  --el1252 latch timestamp readback with per-channel edge statistics
- register access unified in regs.rs: named bit constants everywhere,
  read-modify-write for enable/activation bytes
- vendored patched ethercrab 0.7.1 (sdo_write_complete, send_raw_coe)

Verified on J1900 (PREEMPT_RT 6.6.135): 600k cycles/600s exact 1 kHz,
tx/rx zero errors, phase_err p50=164us std=5us; EL2202<->EL1252 loopback
edge interval mean 2000.24us std=24.65us.
 2026-07-22 08:55:41 +08:00